The introduction of strain in the channel of a field effect transistor (FET), e.g., metal-insulator-semiconductor FET (MISFET) such as a metal-oxide-semiconductor FET (MOSFET), has been used as a way to boost integrated circuit performance, e.g., drive currents (Idsat).
If the length of the channel is reduced, the threshold voltage turns out to become less well-defined and sub-threshold leakage currents occur. In order to inhibit these effects, the dopant concentration of the channel region is made to increase, and the source and drain are formed in a shallow layer. However, if the dopant concentration of the channel region increases, the carrier mobility decreases as a result of an increased scattering of the carriers, and the performance of the FET declines. Also, the shallow source and drain regions cause an increase of parasitic resistance, further hampering the performance. Strained silicon technology enhances carrier mobility in both n-channel and p-channel silicon devices, and thus improves device speed and performance. A relatively simple change in starting materials allows less aggressive scaling of the transistor's gate length and oxide thickness. The increased performance is achieved through higher carrier mobility and reduced source/drain resistance.
FIG. 1 comprises a diagram 100 illustrating the effect of global strain on performance as a function of the channel length L, and a diagram 102 illustrating the effect of local strain on the performance as a function of the channel length L. These diagrams suggest that, for shorter transistor gate lengths, the benefit of global strain decreases, whereas that of local strain increases (Source: Interuniversity Microelectronics Centre (IMEC)).
There are two basic approaches to introducing strain into the transistor's channel: a global approach and a local approach. Bi-axial global strain (also referred to as: substrate-induced strain) is created over the whole wafer. Uni-axial local strain is realized locally, in the transistor's channel.
A first example of uni-axial strain technologies use compressive nitride and tensile nitride layers, deposited over the gates of p-channel FET and n-channel FET devices, respectively. This uniaxial type of strain is optimized to exert strain primarily in the direction along the channel. Because these liners also function as etch stops for the contact etch, this approach, when used on both transistors, is called a dual etch-stop liner (dESL).
A second example of a uni-axial strain technology is called stress memorization. This technology is similar to the liner technique discussed above, but the liner films are sacrificial. Stress is memorized into the device by depositing a film over the gate or source/drain region, performing the dopant activation anneal, and then removing the film. This technique is more complex, and has mostly involved the use of nitride or oxide films to memorize tensile strain in n-channel FETs. A key issue with stress memorization is achieving the desired nMOS performance enhancement without degrading pMOS performance.
A third example of a uni-axial stress technology involves etching out the source/drain area and replacing it with a lattice-mismatched material such as epitaxial SiGe in p-channel FETs and epitaxial SiC in n-channel FETs. Because of the epitaxial deposition technique, the germanium or carbon atoms replace silicon atoms in the lattice (rather than forming the compound SiGe or SiC). Germanium atoms are slightly larger than the lattice constant of silicon, as a result of which SiGe on silicon exerts compressive strain on the silicon channel. Carbon has a much smaller lattice constant, as a result of which silicon containing even a small amount of carbon exerts significant tensile stress on the channel.
An example of a bi-axial stress technology for fully strained silicon-on-insulator (SOI) wafers, as well as for strained silicon on SiGe on insulator (sGOI) wafers, uses the building in of strain into the entire active area of the device. For strained silicon grown on a relaxed SiGe (20%) layer, a 1% silicon lattice deformation results in bi-axial stress. Mobility enhancement is primarily for the nMOS device, though with higher germanium concentration, pMOS improvements are possible.
For more details, please see, e.g., “Strained Silicon: Essential for 45 nm”, Laura Peters, Semiconductor International, Mar. 1, 2007; “A 90 nm High Volume Manufacturing Logic Technology Featuring Novel 45 nm Gate Length Strained Silicon CMOS Transistors”, T. Ghani et al., Proc. IEDM Conf., 2003, pp. 978-980; and “Key Differences For Process-induced Uniaxial vs. Substrate-induced Biaxial Stressed Si and Ge Channel MOSFETs”, S. E. Thompson et al., Proc. IEDM Conf., 2004, pp. 221-224.
Examples of the global approach are disclosed in, e.g., US patent application publication US 20050020094, herein incorporated by reference. Another example is disclosed in Japanese patent abstract publication 2007-250664, which addresses improving performance of a transistor. According to the latter publication, the semiconductor device is provided with a semiconductor chip on which the transistor is formed, first mold resin for resin-sealing a surface-side of the semiconductor chip, and second mold resin for resin-sealing a rear-side of the semiconductor chip. A thermal expansion coefficient of the first mold resin differs from that of the second mold resin. The whole semiconductor chip is physically bent by a difference of contraction forces when the first and second mold resins are cooled. Distortion is introduced into a channel region of the semiconductor chip, thus improving performance.
Examples of the local approach are disclosed in, e.g., US patent application publications US 20070108532 and US 20060160314, both incorporated herein by reference.